Hicks and induced innovation: why power delivery is AI's new frontier

On October 21, 2026, at GTC Berlin, Infineon and NVIDIA announced an extension of their collaboration on 800 volt direct current (VDC) power-conversion architectures for AI data centers. The announcement builds on work begun in May and extended in October 2025 on serviceable, hot-swappable 800 VDC server racks, and now adds power-path protection that will let future server boards run directly on this voltage.

The technical detail is worth dwelling on: at the heart of the system, a high-voltage intermediate bus converter (IBC) steps the main 800 V bus down to an intermediate voltage, itself converted downstream into the rails AI processors consume. Infineon's gallium nitride (GaN) devices, paired with its PSoC Control C3 and EiceDRIVER product families, enable IBC switching frequencies of up to 1 MHz — far above what conventional silicon components achieve. That switching speed mechanically shrinks magnetics and lowers board height, a parameter that has become critical as per-rack power climbs toward the megawatt range.

What stands out in this announcement is that it does not stem from a compute-capacity problem but from an energy-delivery problem inside the rack itself. The scarce factor is no longer only compute silicon — it is increasingly, in parallel, power silicon: the capacity to convert, distribute, and remove the heat of rising electrical power within a volume that is not itself growing.

This is precisely the mechanism economist John Hicks described in The Theory of Wages (1932): when the relative price of one production factor rises against others, that scarcity mechanically induces innovation directed at economizing that specific factor, rather than generic innovation. Hicks reasoned about labor-capital substitution; the mechanism transposes here almost term for term. As AI compute growth bumps up against usable electrical power per unit of volume — rather than simply the number of GPUs produced — the implicit price of that usable power (space, thermal budget, conversion losses) rises faster than that of raw compute. That relative rise induces targeted innovation: not faster chips, but more efficient power semiconductors.

One point Hicks's framework alone does not explain is worth adding: this power constraint does not operate at a single level. The already-documented bottleneck is the external electrical grid — interconnection, queue times, transformer capacity, topics this letter has covered through the year. The Infineon-NVIDIA announcement shows the same relative-scarcity mechanism now operating at the scale of the rack itself, a much finer grain. Induced innovation does not happen once at the macro (grid) level; it recurs at every scale where the power factor becomes locally binding.

A second point, original to this analysis rather than drawn from Hicks: the response here takes the form of a bilateral co-design alliance between a power-semiconductor maker and a GPU maker, rather than classic market innovation where each supplier optimizes its own component independently. The reason lies in the nature of the problem: the voltage architecture spans silicon, boards, and racks simultaneously, creating specification uncertainty and highly specific assets that are costly to coordinate through a one-off market or licensing transaction. The alliance internalizes that coordination rather than leaving it to the market.

For the sectors this letter covers — aerospace & defense, energy & O&G, luxury & cosmetics, industry — the practical implication goes beyond technical curiosity. Any company sizing AI infrastructure investment today (simulation, digital twins, personalization engines, proprietary model training) on GPU availability alone risks underestimating another binding factor: the availability timeline of the power architectures actually needed to run that compute at full load within available space.

Hicks's lesson, nearly a century later, remains a useful predictive tool: each factor that in turn becomes the binding constraint triggers its own wave of induced innovation. After compute, after the external power grid, it is now power conversion inside the rack. Nothing suggests this is the last step — cooling and memory bandwidth are already identified candidates for the next one.